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1/31 ST20196 february 2005 1overview the ST20196 is the digital component of the st20190 utopia chipset. the chipset allows equipment manufacturers to develop flexible plat- forms showing high performance, fully leveraging the adsl2+ 24 mbps wireline speed. these plat- forms can quickly adapt to the rapidly changing re- quirements of the emerging adsl2+ triple-play market covering data, voice and video applica- tions. 2 features adsl2+ dmt modem with embedded controller allowing easy, straight forward integration with external network processors multi-standard support ? g.992.1 annexa,b,c (sbm/dbm) & i ? g.992.2 - g.lite ? g.992.3 annexa,b,i,j,l (extended reach), m (double upstream) ? g.992.4 - g.lite.bis ? g.992.5 annexa,b,c,i,j,m ? ansi t1.413 issue2 ? etsi ts 101 388 adsl-over-isdn ds bitrates above 24 mbps and us bitrates upto 2.5 mbps in annexm (1.2 in annexa) designed to meet standardized and specific operator requirements. catii functionality with echo canceling and trellis coding advanced equalization techniques like per tone equalization standard utopia level1 and 2 atm interface parallel and serial modem control interface (ctrl-e) for glue-less connection to a management entity. supply voltage : 3.3v and 1.2v typical power consumption : 700mw temperature range : i-range (-40c to 85c) 3 applications medium/high end routers business routers with modular and/or multiple wan access security applications voice and data gateways wireless access points convergence of gateways and ip settopbox home servers with storage capabilities, smart card interfaces, unified mailboxes, ? figure 2. block diagram pmd tc dmt platform network processor st20184 ST20196 splitter & dfe sdram/ optional flash dmt afe utopia processor platform uart gpio irq jtag utopia level 1/ 2 ctrl-e adsl2+ utopia dmt transceiver for cpe applications rev. 1 fi gure 1. p ac k age table 1. order codes part number package ST20196 lbga208 (17x17x1.7mm) lbga208 (17x17x1.7mm)
ST20196 2/31 4 general description the new adsl2+ standards will accelerate broadband applications way beyond always-on data stream- ing, mainly used for web-browsing and e-mailing. internet service providers are exploring several ways to increase their revenues by offering new services and applications and enlarging their customer base. this can be realized using the large number of new features and different annexes of adsl2+. the ST20196 is designed in a main stream digital cmos technology. the major building blocks are the dmt engine including the pmd and tc layer, the arm? microcontroller and the different interfaces like utopia level i&ii, ctrl-e, interfacing to the st20184 and memory. the dmt engine is compliant with the new adsl2+ standards and supports features like diagnostics mode, enhanced power management (l2), 1 bit constellation, relocatable and modulated pilot, ? on top of the mandatory new features, the dmt engine includes several differentiating, advanced and unique techniques like an innovative per tone equalizer (pteq) optimizing short loop and bridge tap per- formances and reducing the impact of rfi in adsl2+ mode. a highly performant echo canceller (ec) and a fully digital clock recovery scheme (tdi) further differen- tiate the st20190 adsl2+ performances. to be prepared for triple-play applications a flexible tc-layer has been implemented. the cached arm? micro-controller allows further improvement of the performances and allows fast and easy integration with the major third party network processors. data is exchanged over the utopia level1 or 2 interface and the commands via the st ctrl-e modem control command protocol. 5 processor platform figure 3. processor platform diagram 5.1 micro-controller the micro-controller is made of an arm946? microprocessor with 8kbytes instruction and 8kbytes data caches. he is connected to 16kbytes internal ram and 512bytes rom. interrupt controller uart timers watchdog gpio controller bridge rom ram sdram controller flash controller dmt platform arm946 tm 8k + 8k ctrl -e ebi ahb apb jtag
3/31 ST20196 5.2 rom and boot procedure the rom contains the boot sequence needed for code download at startup from uart or ctrl-e inter- face. the use of the rom by the arm946? microprocessor is defined by the state of the trom pin dur- ing reset. trom = '1': the processor boots directly from the external flash. trom = '0': the processor boots from internal rom. the communication settings for the uart are then fixed to 38400 bauds, no parity, 8 data bits, 2 stop bits. 5.3 memory interface the ST20196 implements a shared interface for external memories. the sdram and flash i/o pins are muxed by the ebi module table 2. 5.3.1 sdram ST20196 supports sdram access through a sdram controller, which supports ? 16 bit sdram access ? sdram sizes up to 512mbits the sdram controller has a built in refresh timer. refresh and access times can be modified through firmware to support different sdram requirements. all sdram actions are triggered at the rising edge of its clock. timing diagrams for a burst of four 16-bit accesses to 16-bit sdram show the basic behavior of the control signals. figure 4. sdram read access (cas latency = 3 , burst = 4) pin name size type sdram flash e_d[15:0] 16 io d[15:0] d[15:0] e_a[15:0] 16 io a[15:0] (output) a[15:0] (output) s_dqm[1:0] 2 o dqmask[1:0] a[17:16] s_ncas 1 o ncas a18 s_nras 1 o nras a19 sf_nwe 1 o nwe nwr s_clk 1 io clk s_ncs 1 o ncs f_ncs 1 o ncs f_noe 1 o nrd, noe
ST20196 4/31 figure 5. sdram write access (cas latency = 3 , burst = 4) figure 6. sdram interface timing setup and hold time for input signals clock t1 t2 output delay for output signals t3max t3min tri-state timing for tri-state output signals t4min t4max t5min t5max setup and hold time for input signals clock t1 t2 output delay for output signals t3max t3min tri-state timing for tri-state output signals t4min t4max t5min t5max setup and hold time for input signals clock t1 t2 output delay for output signals t3max t3min tri-state timing for tri-state output signals t4min t4max t5min t5max
5/31 ST20196 table 3. note: - the timing values are given for best to worst case operating conditions. - setup and hold times for input signals are based 1.5 ns input transition time. - the output delays are based on 25pf loading capacitance. 5.3.2 flash ST20196 flash interface supports ? 8-bit flash access ? flash sizes up to 8mbit (1m x 8bit) figure 7. flash read timing signal description min. max. s_clk clock sdram clock 35.328 mhz duty cycle 40% 60% s_ncs output t3 output delay from s_clk 2.8 ns 7.5 ns s_nras output t3 output delay from s_clk 2.8 ns 7.5 ns s_ncas output t3 output delay from s_clk 2.8 ns 7.5 ns s_dqm[1:0] output t3 output delay from s_clk 2.8 ns 7.5 ns sf_nwe output t3 output delay from s_clk 2.8 ns 7.5 ns e_a[15:0] output t3 output delay from s_clk 2.8 ns 7.5 ns e_d[15:0] input t1 input setup to s_clk 1 ns - t2 input hold from s_clk 1 ns - e_d[15:0] output t3 output delay from s_clk 2 ns 9.5 ns t4 signal going low impedance from s_clk 2 ns 9.5 ns t5 signal going high impedance from s_clk 2 ns 9.5 ns data valid address valid ncs nrd data addr t asu t ah t dd t dhr t rl t tcssu t csh data valid address valid ncs nrd data addr t asu t ah t dd t dhr data valid address valid ncs nrd data addr t asu t ah t dd t dhr t rl t tcssu t csh
ST20196 6/31 figure 8. flash write timing figure 9. flash chip select timing flash timing parameters, programmable to some extent by steps of clock cycles (typically 35.328mhz). table 4. flash timing parameters 5.4 ctrl-e the ctrl-e interface controller is a generic mailbox system to exchange control and status messages be- tween st-20196 (over ahb bus) and an external controller (over ctrl-e interface). it consists of a mailbox and a physical interface. although the two 8-bit command registers are intended for use in one direction (arm? to ctrl-e or ctrl-e to arm?) they are fully accessible in read and write from both sides. so it is up to the software to guarantee consistency of register values. two control registers only accessible by name min (ns) max (ns) number of clock cycles default min max t cssu 0 - isa_tcssu 4 0 15 t csh 0-isa_harw2015 t rl 0-isa_trl15015 t dd -150 - --- t dhr -40 - --- t dsu 0 - isa_tdsu 12 0 15 t dhw 0-isa_harw2015 t asu 0-isa_tasu4015 t ah 0-isa_harw2015 t ncsc 50 - 5 - - - data valid address valid ncs nrd data addr t asu t ah t dd t dhr t rl t tcssu t csh data valid address valid ncs nrd data addr t asu t ah t dd t dhr data valid address valid ncs nrd data addr t asu t ah t dd t dhr t rl t tcssu t csh ncs t ncsc ncs t ncsc
7/31 ST20196 the arm? core allow configuration of the status update mechanism and of interrupt generation. the ctrl-e physical interface between the mailbox and an external controller is implemented as a generic parallel bus interface. the ctrl-e mailbox and its interfaces are all running synchronous to the ahb clock. figure 10. ctrl-e interface controller principle 5.4.1 ctrl-e mail box the ctrl-e mailbox occupies a 512 byte memory map accessible by the ctrl-e physical interface and by the ahb bus. the mailbox memory map is given in the table below. two addresses are shown in the memory map: ctrle a[8:0] as generated by the ctrl-e physical interface and the lsbs of the ahb address bus ahbaddress[8:0]. the two configuration registers ctrl-e control and ctrl-e interrupt are only accessi- ble by the ahb bus. the mailbox interrupt controller generates two interrup ts: an internal interrupt towards the arm? interrupt controller (ctrl-e intarm), and an external interrupt towards the external controller (ctrl-e intext). depend- ing on the configuration an interrupt-based or polling-based communication protocol can be implemented. table 5. ctrl-e mail box memory map field arm? address ctrl-e address size function txcommand 000h 000h 8 transmit commands rxcommand 001h 001h 8 receive commands txcomav 002h 002h 1 1 = tx command is available rxcomav 003h 003h 1 1 = rx command is available semaphore 004h 004h 2 semaphore data buffer 005h ? 1ffh 005h ? 1ffh 8 507 x 8bit data buffer statusctrl 200h na 8 status control register interruptctrl 201h na 8 interrupt control ctrle mailbox ctrl-e data buffer 512 bytes semaphore rxcomav txcomav rxcomman d txcommand ctrl-e physical interface parallel protocol ahb int. controller irq-fiq io?s ctrle mailbox ctrl-e data buffer 512 bytes semaphore rxcomav txcomav rxcomman d txcommand ctrl-e physical interface parallel protocol ahb int. controller irq-fiq io?s
ST20196 8/31 5.4.2 ctrl-e semaphore a simple semaphore mechanism is provided to allow control of the data consistency of the ctrl-e data buffer and command registers. if there would be unlimited accesses to all mailbox addresses over the two interfaces by the two independent controllers there would be no possibility to implement a semaphore mechanism in software. therefore one mailbox address is defined as a two-bit semaphore register pro- tected by control logic to prevent illegal write accesses to this register. before a read/write access by one of the two interfaces (ahb or ctrl-e) this interface should perform a 'p- operation' on the semaphore. after a read or write of the data buffer, the interface should do a 'v-operation' releasing the semaphore. p and v operations are performed by write and read accesses to the sema- phore register. the semaphore will be updated as shown in table 10. each semaphore operation (p or v) consists of two consecutive actions: a. write the correct value to the semaphore address (see table below) b. read the value in the semaphore address. if the value read is different from the value written the p or v operation was not successful and should be tried again. table 6. semaphore p and v operations the data buffers can be accessed without using the semaphore mechanism if data consistency is guar- anteed in another way. if other values are written to the semaphore address than the values listed, the write will not be performed. 5.4.3 ctrl-e physical interface physical interface implements a generic parallel interface with 9 bit address and 8 bit data bus. two par- allel bus modes are defined to support both motorola-compatible and intel-compatible timing and control signals. this interface specification is compliant to atm forum physical layer control parallel interface. the parallel bus mode section is done with the c_mode input pin: table 7. the two parallel bus modes differ only in the definition of 3 control signals: ? bus mode 0 provides a read/write selector, a data strobe and a ready acknowledge. ? bus mode 1 provides a read strobe, a write strobe and a ready acknowledge. the signal definition is shown in following table: semaphore originator value written free taken by arm? taken by ctrl-e 00 01 11 parm?01 01 01 11 ctrl-e 11 11 01 11 varm?00 00 00 11 ctrl-e 00 00 01 00 c_mode description 0 motorola-type parallel interface 1 intel-type parallel interface (sram like)
9/31 ST20196 table 8. all input signals are registered internally using the ahb clock. but there is no need to synchronize the in- terface to the main clock. due to this fact, the interface will behave faster in case of ahb higher clock frequency. all timings are preliminary. intel-like motorola-like type description c_a[8:0] c_a[8:0] i address c_d[7:0] c_d[7:0] io data bus c_notcs c_notcs i chip select c_notint c_notint oz interrupt output (inverted) c_notwr c_rd/notwr i write command or write enable c_notrd c_notds i read command or data strobe c_notrdy c_notdtack oz ready signal or ack c_mode c_mode i mode select (= 0 or 1 )
ST20196 10/31 5.4.4 ctrl-e write access figure 11. ctrl-e write access timing diagram table 9. ctrl-e write access timing (*): this is a minimal value. in case c_notdtack(c_notrdy) is used to synchronize the process, one should wait until c_notdtack (c_notrdy) becomes low (t10) (1): timings fully defined by the ctrl-e master: these timings are considered as necessary to make the interface work (2): timings fully dependable of the ctrl-e slave (3): 10ns is added to the theoretical value in order to include the input and output delays symbol description ahb clock cycles ahb at 35.328mhz (ns) min max min max t1 (1) c_a setup to c_notds (c_notwr) low 0 - 0 - t2 (1) c_notcs, c_rd/notwr setup to c_notds (c_notwr) low 0 - 0 - t3 (1) c_notds (c_notwr) pulse width 5 (*) - 153 (3) - t4 (1) c_d setup to c_notds (c_notwr) high 0 - 0 - t5 (1) c_a, c_d hold from c_notds (c_notwr) high 0 - 0 - t6 (2) c_notdtack (c_notrdy) valid from c_notds (c_notwr ) low - 0 - 10 (3) t7 (2) c_notdtack (c_notrdy) tri-state from c_notds (c_notwr) high -0 10 (3) t8 (1) c_notcs, c_rd/notwr hold from c_notds (c_notwr) high 0 - 0 - t9 (1) c_notcs high to c_notcs low 3 - 96 (3) - t10 (2) c_notds low to c_notdtack low 5 6 143 182 (3) t10
11/31 ST20196 5.4.5 ctrl-e read access figure 12. ctrl-e read access timing diagram table 10. ctrl-e read access timing (1): timings fully defined by the ctrl-e master: these timings are considered as necessary to make the interface work (2): timings fully dependable of the ctrl-e slave (3): 10ns was added to the theoretical value in order to include the input and output delays. symbol description ahb clock cycles ahb at 35.328mhz (ns) min max min max t1 (1) c_a setup to c_notds (c_notrd) low 0 - 0 - t2 (1) c_notcs, c_rd/notwr setup to c_notds (c_notrd) low 0 - 0 - t3 (1) c_notds (c_notrd) pulse width 7 - 210 (3) - t4 (2) c_d valid from c_notdtack (c_notrdy) low - 0 - 5 t5 (1) c_a hold from c_notds (c_notrd) high 0 0 t6 (2) c_notdtack (c_notrdy) volid from c_notds (c_notrd) high - 0 - 10 (3) t7 (2) c_notdtack (c_notrdy) tri-state from c_notds(c_notrd) high -0 - 10 (3) t8 (1) c_notcs, c_rd/notwr hold from c_notds (c_notrd) high 0 - 0 - t9 (2) data tri-state from c_notds (c_notrd) high 3 4 86 124 (3) t10 (2) data tri-state from c_notcs high 0 4 0 124 (3) t11 (1) c_notcs high to c_notcs low (min. time between 2 accesses) 3 - 86 - t12 (2) c_notds low to c_notrdy low 6 7 172 210 (3) t12
ST20196 12/31 5.5 peripherals ST20196 processor platform includes different peripherals located on a second level bus, connected to the main ahb bus through a bridge. 5.5.1 watchdog the watchdog is actually a 32-bit real-time counter configured as watchdog. it generates both an interrupt signal sent to the interrupt controllers and a reset signal sent to the reset controller. 5.5.2 real time counters there are 2 general-purpose 32-bit real time counters. it consists of single 32-bit down-counters that gen- erate interrupts if the counters reach zero. 5.5.3 interrupt controllers there are 2 interrupt controllers. one is connected with the arm? irq and one with the arm? fiq. all st-20196 interrupts are connected at the same time to both controllers to allow sw to decide which ones to handle as fast and which to handle as slow interrupts. 5.5.4 uart there is one uart for rs232 interfacing to external systems. the uart is capable of full-duplex data transfer at user defined baud rates. most common baud rates are supported. fifos with configurable depth store the received and the data to be transmitted. the uart offers parity checking, stop bit length control and hardware handshake. when booting from the internal rom, the communication settings are: 38400 bauds, no parity, 8 data bits, 2 stop bits. 5.5.5 gpio controller there is 1 gpio controller driving 8 external gpio's. 6 clocking scheme figure 13. clocking scheme internal clocks are derived from the mclk input clock via a pll. 7 dmt platform the following section essentially describes the sequence of actions performed by the dmt platform. 7.1 dmt-afe (st20184) the dmt-afe module is taking care of the interface with the analog front end device. the module is sup- porting only the st20184 device. in the receive direction, the dmt-afe module gets the signal multiplexed on 10 inputs and transmit it with pll mclk 141.312mhz dmt platform 70.656mhz dmt platform 70.656mhz micro controller 35.328mhz ahb bus and peripherals 35.328mhz 35.328mhz dmt-afe pll mclk 141.312mhz dmt platform 70.656mhz dmt platform 70.656mhz micro controller 35.328mhz ahb bus and peripherals 35.328mhz 35.328mhz dmt-afe
13/31 ST20196 a first decimation to the dmt-pmd module. in the transmit direction, the dmt-afe module transfers the signal multiplexed on 4 output signals. the module includes test loop-backs. 7.1.1 dmt-afe interface signals figure 14. table 11. 7.1.2 dmt-afe interface timing figure 15. afe receive data bus figure 16. afe transmit data bus signal description mclk 35.328mhz clock. clwd synchronization signal generated on mclk rising edge (in st-20184) and sampled on mclk falling edge (in st-20196). afrxd[9:0] afe receive data bus: 5 pdm?s at 70mhz multiplexed on 10 pins at 35mhz. signals are generated on mclk rising edge (in st-20184) and sampled on mclk falling edge (in st-20196). aftxd[3:0] afe transmit data bus: 16bit samples at 8.8mhz, split on 4*4 signals at 35mhz, synchronized with clwd. signal are generated on mclk rising edge (in st-20196) and sampled on mclk rising edge (in st-20184). afe_ctr_in afe control response serial bit. sampled on mclk rising edge when clwd goes high. afe_ctr_out afe control transmit serial bit. generated on mclk rising edge when clwd goes low. st 20184 st 20196 afrxd[9:0] afe_ctr_out afe_ctr_in aftxd[3:0] mclk clwd d ata ctr l s yn c d at a ctr l sy nc mclk afrxd mclk afrxd mclk clwd aftxd n0n1n2n3n0 n3 mclk clwd aftxd n0n1n2n3n0 n3
ST20196 14/31 figure 17. afe control write protocol the write protocol is composed of 5 parts, at the rate defined by clwd: ? 1 leading start bit ? 4 bits representing an address, msb first ? 1 logic zero bit to indicate it is a write access ? 12 bits of data, msb first ? 16 stop bits figure 18. afe control read protocol the read protocol is composed of 5 parts, at the rate defined by clwd: ? 1 leading start bit on afe_ctr_out ? 4 bits representing an address, msb first, on afe_ctr_out ? 1 logic one bit to indicate it is a read access, on afe_ctr_out ? 12 bits, listen state on afe_ctr_out, data msb first on afe_ctr_in ? 16 stop bits on afe_ctr_out table 12. note: - the timing values are given for best to worst case operating conditions. - setup and hold times for input signals are based 1.5 ns input transition time. - the output delays are based on 25pf loading capacitance. signal description min max afrxd[9:0] input setup time to mclk falling edge 0.5 ns - hold time from mclk falling edge 0.2 ns - aftxd[3:0] output output delay from mclk rising edge 0.5 ns 4 ns clwd input setup time to mclk falling edge 0.5 ns - hold time from mclk falling edge 0.2 ns - afe_ctr_out output output delay from mclk rising edge 0.5 ns 4 ns afe_ctr_in input setup time to mclk rising edge 0.5 ns - hold time from mclk rising edge 0.2 ns -
15/31 ST20196 7.2 dmt-pmd figure 19. 7.2.1 time domain processing (tdp) the tdp contains in the receive direction: time domain interpolator (tdi), iir filters, decimators and echo suppression. the tdi receives 8.8 mhz (17.6 mhz for adsl+) samples and performs a lagrange inter- polation. the decimators receives then the interpolated samples and reduces this rate to 2.2 mhz (4.4 mhz in adsl+). in the transmit direction, the tdp includes: side-lobe filtering, clipping, delay equalization, interpolation and time domain interpolation. the side-lobe filtering and delay equalization are implemented by iir filters, reducing the effect of echo in fdm systems. clipping is a statistical process limiting the amplitude of the output signal, optimizing the dynamic range of the afe. the interpolator receives data at 2.2 mhz and generates samples at a rate of 8.8 mhz. the transmitted samples are interpolated. the echo is computed via a 256 taps fir. 7.2.2 frequency domain processing (fdp) in rx path, the module is ba sed on programmable dsp and fft m odule working as a coprocessor. the instruction set enables functions like fft, per tone equalizer (pteq), scaling, and frequency equal- ization (feq). this block implements the core of the dmt algorithm as specified in ansi t1.413. the 512-points fft (1024 points in adsl+) transforms the time-domain dmt symbol into a frequency domain representat ion which can be further decoded by t he subsequent dem apping stages. after fft and pteq blocks - an essentially ici (inter carrier interference) - free carrier information stream has been ob- tained. this stream is still affected by carrier specific channel distortion resulting in an attenuation of the signal amplitude and a rotation of the signal phase. to compensate for these effects, the fft+pteq is followed by a frequency domain equalizer (feq). in case of annex c mode, 2 different feq coefficient tables are used for fext and next. in the tx path, the ifft transforms the dmt symbol generated in the frequency domain by the mapper into a time domain representation. the ifft block is preceded by a fine tune gain. in case of annex c mode, 2 different ftg coefficient tables are used for fext and next. 7.2.3 constellation domain processing (cdp): (de)mapper, monitor, trellis (de)coding the demapper converts the constellation points computed by the fdp to a list of bits. this essentially con- sists in identifying a point in a 2d qam constellation plane. the demapper supports trellis coded demod- ulation and provides a viterbi maximum likelihood estimator. when the trellis is active, the demapper receives an indication for the most likely constellation subset to be used. in the transmit direction, the mapper performs the inverse operation, mapping a block of bits into one con- stellation point (in a complex x+jy representation) wh ich is passed to the ifft bl ock. the trellis encoder tdp fdp cdp from dtm -tc to dtm-afe scheduler clock recovery fir coefficients training and tracking upstream traffic downstream traffic from dtm-afe to dtm-tc
ST20196 16/31 generates redundant bits to improve the robustness of the transmission, using a 4-dimensional trellis coded modulation scheme. the monitor computes error parameters for carriers specified in the demapper process. those parame- ters can be used for updates of adaptive filters coefficients, clock phase adjustments, error detection, etc. a series of values is constantly monitored, such as signal power, pilot phase deviations, symbol erasures generation, loss of frame, etc. a special reverb-segue detector allows an easy detection of l2-exit sequence in adsl2(+) applications. in case of annex c mode, 2 different (de)mapper tables are used for fext and next, as 2 different mon- itoring memories for fext and next. 7.2.4 fir coefficients training and tracking feq coefficients are trained and kept up-to-date by a specific block reading the carrier errors coming out of the monitoring process. the echo-canceller and pteq fir coefficients are updates are in frequency domain via a dedicated dsp based on a floating point data-path. 7.2.5 clock recovery a digital pll module receives a metric for the phase error of the pilot tone. in general, the clock frequen- cies at co and cpe do not match exactly. the phase error is filtered and integrated by a low pass filter, yielding an estimation of the frequency offset. the phase error can be compensated in the time domain by interpolating samples 7.2.6 dmt symbol timing unit (dstu) the dstu interfaces with various modules. it consists of a real time and a scheduler module. the real time unit generates a time base for the dmt symbols (sample counter), super-frames (symbol counter) and hyper-frames (sync counter). the time bases can be modified by various control features. they are continuously fine tuned by the dpll module. the dstu schedulers execute a program, controlled by pro- gram op-codes and a set of variables, the most important of which are real time counters. the transmit and receive sequencers are completely independent and run different programs. an independent set of variables is assigned to each of them. the sequencer programs can be updated in real time. in case of annex c mode, the dstu take care also of the hyper-frame synchronization, the table switch for fext and next period and the control of the dummy bits insertion/extraction. 7.3 dmt-tc figure 20. interleaver read- solomon scrambler adsl framer atm framer from dtm-utopia to dtm-pmd micro controller mini platform event counter upstream traffic downstream traffic from dtm-pmd to dtm-utopia tps-tc pms-tc
17/31 ST20196 7.3.1 interleaver, reed-solomon, scrambler, adsl framer based on an arm7tdmi? processor associated with a dedicated programmable data-path. these functions relate to byte oriented data streams. they are completely described in ansi t1.413. ad- ditions described in the issue 2 of this specification are also supported. the data received from the dmt-pmd is split into two paths: interleaved and non-interleaved data flow g.dmt mode, latency 0 and latency 1 data flow in g.dmt.bis mode. in case of annex c mode, a rate adaptation is also performed in order to average the different bit rates during fext/next at pmd layer into a fixed rate at tc layer. in the receive direction, the de-interleaving is used to increase the error correcting capability of block codes for error bursts. after de-interleaving (if applicable), the data flow enters a reed-solomon error cor- recting code decoder, able to correct a number of bytes containing bit errors. the decoder also uses the information of previous receiving stages that may have detected the errored bytes and have labeled them with an "erasure" indication. after leaving the reed-solomon decoder, the corrected byte stream is de- scrambled and the crc verified. after, the data flows are processed by programmable machine. the different framing types (g.dmt and g.dmt.bis) are managed by specific micro-codes loaded into the byte oriented machine. the different type of data is routed toward the atm framer or the adsl-message-manager. the adsl-message-manager take care of eoc bytes (embedded operations channel), aoc bytes (adsl overhead control), hdlc bytes and the indicators bits. in the transmit direction, similar tasks are performed. 7.3.2 atm framer in the receive direction, two byte streams (fast/slow or bearer channel 0/1) are received from the pms-tc unit. when atm cells are transported, this block provides basic cell functions such as cell synchronization, cell payload descrambling, idle/unassigned cell filter, cell header error correction (hec) and detection. the cell processing happens according to itu-t i.163 standard. provision is also made for ber measure- ments at this atm cell level. the module provide some flexibility in order to be able to transport non atm cell oriented byte streams, to be able to support ima system and to be able to support bonding system. atm cells are stored in fifo's from which they are extracted by a utopia level 1 interface or a utopia level 2 interface. in the transmit direction, similar tasks are performed, including idle insertion. 7.3.3 micro controller mini-platform and event counter the dmt-tc module is controlled by a local processor platform containing an arm7tdmi?, an interrupt controller and some memories. the event counter module accumulates dmt-tc statistics: reed-solomon corrections, crc errors, hec errors ? 7.3.4 ntr based on the information received within the adsl frame and based on the digital dpll output, a network reference clock (typically 8 khz) can be regenerated. a low-pass filtering is performed on the local micro controller. 7.4 dmt-utopia reference spec: utopia specification. level1, versi on 2.01, march 1994. level 2, version 1.0, june 1995. see www.atmforum.com the ST20196 supports both utopia level 2 and level 1 cell based data interface between the phy layer (within ST20196) and the atm layer chip. the atm layer is considered as the reference and all transfers are seen from the atm layer's point of view. hence the transmit direction would be data flow from atm layer to the phy layer, while data flow from phy layer to atm layer is referred to as receive direction. in both cases atm layer is the master.
ST20196 18/31 figure 21. signals at utopia level2 receive interface table 13. receive interface signals figure 22. signals at utopia level2 transmit interface table 14. transmit interface signal signals are latched on the rising edge of their respective clocks: rxclk or txclk. the utopia level 2 specification assigns 5 address lines for receive and transmit. st-20196 provides the 2 lsb rx and tx address lines to support 2 atm channels and the required "idle" channel. the 3 msb receive and transmit address lines are tied high internally, so that 3 addresses are available: 28, 29 and 30. when the 2 lsb address lines are high ('11') the st-20196 atm channel is set to "idle" channel and 7 addresses are available for other devices (addresses 3, 7, 11, 15, 19, 23 and 27). signal description rxaddr[1:0] address used to select the port that will be active or polled rxdata[7:0] receive data bus, atm cell data to atm layer rxsoc start of cell, indicates the first byte of the cell rxenb enable (active low), indicates to the st-20196 when to output cell data rxclav cell available, indicates to the atm layer that the st-20196 has cell ready for transfer rxclk receive byte clock generated by atm layer signal description txaddr[1:0] address used to select the port that will be active or polled txdata[7:0] transmit data bus, atm cell data from atm layer txsoc start of cell, indicates the first byte of the cell txenb enable (active low), indicates to the st-20196 that txdata and txsoc are valid txclav cell available, indicates to the atm layer that the st-20196 has cell ready to accept cell txclk transmit byte clock generated by atm layer ST20196 network processor u t o p ia rxaddr[1:0] rxenb rxclk rxdata[7:0] rxsoc rxclav u topia network processor uto p ia txaddr[1:0] txenb txclk txdata[7:0] txsoc txclav u topia ST20196
19/31 ST20196 7.4.1 utopia interface timing figure 23. utopia interface timing diagram table 15. note: "the timing values are given for best to worst case operating conditions. "setup and hold times for input signals are based 1.5 ns input transition time. "the output delays are based on 25pf loading capacitance. signal description min. max. rxclk clock rxclk frequency 1mhz 50mhz rxclk duty cycle 40% 60% rxenb input t1 input setup to rxclk 4 ns - t2 input hold from rxclk for rxenb 1.6 ns - rxaddr[1:0] input t1 input setup to rxclk 4 ns - t2 input hold from rxclk for rxaddr 1 ns - rxclav output t3 output delay from rxclk 1.5 ns 12 ns t4 signal going low impedance from rxclk 1.5 ns 12 ns t5 signal going high impedance from rxclk 1.5 ns 12 ns rxsoc output t3 output delay from rxclk 1.5 ns 12 ns t4 signal going low impedance from rxclk 1.5 ns 12 ns t5 signal going high impedance from rxclk 1.5 ns 12 ns rxdata[7:0] output t3 output delay from rxclk 1.5 ns 12 ns t4 signal going low impedance from rxclk 1.5 ns 12 ns t5 signal going high impedance from rxclk 1.5 ns 12 ns txclk clock txclk frequency 1mhz 50mhz txclk duty cycle 40% 60% txenb input t1 input setup to txclk 4 ns - t2 input hold from txclk 1 ns - txsoc input t1 input setup to txclk 4 ns - t2 input hold from txclk 1 ns - txaddr[1:0] input t1 input setup to txclk 4 ns - t2 input hold from txclk 1 ns - txdata[7:0] input t1 input setup to txclk 4 ns - t2 input hold from txclk 1 ns - txclav output t3 output delay from txclk 1.5 ns 12 ns t4 signal going low impedance from txclk 1.5 ns 12 ns t5 signal going high impedance from txclk 1.5 ns 12 ns setup and hold time for input signals clock t1 t2 output delay for output signals t3max t3min tri-state timing for tri-state output signals t4min t4max t5min t5max setup and hold time for input signals clock t1 t2 output delay for output signals t3max t3min tri-state timing for tri-state output signals t4min t4max t5min t5max setup and hold time for input signals clock t1 t2 output delay for output signals t3max t3min tri-state timing for tri-state output signals t4min t4max t5min t5max
ST20196 20/31 8 electrical data - general specifications 8.1 absolute maximum ratings maximum voltage stress without impacting the reliability of the device: 8.2 operating conditions operating ranges define the limits for functional operation and schematic characteristics of the device. functionality outside these limits is not implied. 8.3 power dissipation power dissipation corresponding to an adsl2+ "show-time" state with maximum throughput and all dmt features activated. '0%': vdd-io = 3.3v, vdd-core = 1.2v '5%': vdd-io = 3.47v, vdd-core = 1.26v '10%': vdd-io = 3.6v, vdd-core = 1.32v 8.4 thermal characteristics, as per jedec jsd51 8.5 io characteristics table 16. general interface electrical characteristics* notes: 1. 1.08v is the minimum core voltage to fit electrical spec ifications. but these ios functional for a core voltage down to 0.8v (and even 0.7v if vdde3v3 does not exceed 3.3v for 3.3v capable ios) 2. human body model 3. the 3.3v ios are functional until 2.2v. 4. the 3.3v ios comply with the eia/jedec standard jesd8-b symbol parameter value unit vdd io power supply 3.6 v vdd core power supply 1.32 v symbol parameter min. typ. max. unit vdd io power supply 3.0 3.3 3.6 v vdd core power supply 1.08 1.2 1.32 v tamb ambient temperature -40 85 degc tj junction temperature -40 125 degc +0% 25degc +5% 70degc +5% 85degc +10% 70degc +10% 85degc total power (mw) 700 950 1000 1050 1150 i-core (ma) 520 700 740 740 800 i-io (ma) 17 18.5 18.5 20 20 thermal resistance junction to ambient theta j-a 38.4 degc/w thermal resistance junction to case theta j-c 9.1 degc/w psi junction to top case psi j-c 1 degc/w symbol parameter test conditions min typ max unit vdd core power supply voltage 1.08 1) 1.2 1.32 v vdde3v3 3.3v io power supply voltage 3 3.3 3.6 v t j operating junction temperature -40 25 85 c ilatchup i/o latch-up current 200 ma vesd 2) electrostatic protection leakage < 1u 4000 v 2
21/31 ST20196 table 17. lvttl dc input specification (3v ST20196 22/31 figure 24. typical power-up sequence vdd-core or vdd-io nreset mclk pll power-up pll powered-up after 4096 mclk rising edges pll locked pll lock time internal clocks vdd-io or vdd-core min. 0 us min. 200 us 116 us recommanded to keep the device under reset until mclk is stabilised ~15 us 7 us external internal internal nreset?s internal reset lines released after 256 mclk rising edges, starting from locked pll
23/31 ST20196 9 pin description table 20. pin description ball signal name pad type description b1 nreset in pull-up schmit chip reset, active low. minimum reset pulse width: 30 ns. with shorter pulse, st-20196 behavior is unpredictable. n13 mclk in schmit master clock 35.328 mhz c3 procspeed in arm946? clock speed. to be strapped to vdd d3 ahbspeed in internal ahb bus speed. to be strapped to gnd d1 trom in boot mode: gnd: from internal rom vdd: from external flash eprom r14 irq in general purpose irq used for dying gasp detection j14 ntr out tri-state ntr, 8khz network reference clock e1 pa[0] inout gpio a bit[0] d2 pa[1] inout gpio a bit[1] (used for led indication) e4 pa[2] inout gpio a bit[2] (used for led indication) e2 pa[3] inout gpio a bit[3] g3 pa[4] inout gpio a bit[4] g4 pa[5] inout gpio a bit[5] h1 (h2) pa[6] inout gpio a bit[6] h3 (j3) pa[7] inout gpio a bit[7] c2 f_ncs out tri-state flash chip select n10 f_noe out tri-state flash output enable t11 s_ncs out tri-state sdram chip select e3 s_clk inout sdram clock, 35.328mhz f1 (f2) sf_nwe out tri-state sdram-flash write enable f3 s_nras out tri-state sdram row address strobe / flash a19 f4 s_ncas out tri-state sdram column address strobe / flash a18 g1 s_dqm[0] out tri-state sdram lower dq mask enable / flash a17 g2 s_dqm[1] out tri-state sdram upper dq mask enable / flash a16 r3 (p4) e_a[0] inout ebi address bus t1 (t2) e_a[1] inout ebi address bus n4 (n3) e_a[2] inout ebi address bus p2 (p3) e_a[3] inout ebi address bus r1 (r2) e_a[4] inout ebi address bus m3 (m4) e_a[5] inout ebi address bus p1 (n2) e_a[6] inout ebi address bus n1 e_a[7] inout ebi address bus l4 e_a[8] inout ebi address bus m2 e_a[9] inout ebi address bus m1 e_a[10] inout ebi address bus l3 e_a[11] inout ebi address bus l2 e_a[12] inout ebi address bus l1 e_a[13] inout ebi address bus
ST20196 24/31 ball signal name pad type description k4 e_a[14] inout ebi address bus k3 e_a[15] inout ebi address bus t3 (r4) e_d[0] inout ebi data bus p5 (n5) e_d[1] inout ebi data bus t4 (r5) e_d[2] inout ebi data bus p6 (n6) e_d[3] inout ebi data bus t5 (r6) e_d[4] inout ebi data bus t7 (t6) e_d[5] inout ebi data bus r7 (p7) e_d[6] inout ebi data bus n7 (p8) e_d[7] inout ebi data bus t8 e_d[8] inout ebi data bus r8 e_d[9] inout ebi data bus t9 e_d[10] inout ebi data bus r9 e_d[11] inout ebi data bus p9 e_d[12] inout ebi data bus t10 e_d[13] inout ebi data bus r10 e_d[14] inout ebi data bus p10 e_d[15] inout ebi data bus p15 afrxd[0] in afe receive data bus r16 afrxd[1] in afe receive data bus p14 afrxd[2] in afe receive data bus r15 afrxd[3] in afe receive data bus t13 afrxd[4] in afe receive data bus n11 afrxd[5] in afe receive data bus r12 afrxd[6] in afe receive data bus t12 afrxd[7] in afe receive data bus p11 afrxd[8] in afe receive data bus r11 afrxd[9] in afe receive data bus t15 aftxd[0] out tri-state afe transmit data bus r13 aftxd[1] out tri-state afe transmit data bus t14 aftxd[2] out tri-state afe transmit data bus p12 aftxd[3] out tri-state afe transmit data bus t16 clwd in afe data word clock p13 afe_ctr_out out tri-state afe serial control data out n12 afe_ctrl_in in afe serial control data in b5 power_down out tri-state afe power down p16 txaddr[0] in utopia tx address n14 txaddr[1] in utopia tx address n15 txdata[0] in utopia tx data m13 txdata[1] in utopia tx data n16 txdata[2] in utopia tx data m15 txdata[3] in utopia tx data m14 txdata[4] in utopia tx data table 20. pin description (continued)
25/31 ST20196 ball signal name pad type description l13 txdata[5] in utopia tx data m16 txdata[6] in utopia tx data l16 txdata[7] in utopia tx data l15 txenb in utopia tx enable l14 txclav out tri-state utopia tx cell available k16 txsoc in utopia tx start of cell k15 txclk in schmit utopia tx clock g13 rxaddr[0] in utopia rx address c16 rxaddr[1] in utopia rx address e14 rxdata[0] out tri-state utopia rx data d16 rxdata[1] out tri-state utopia rx data f13 rxdata[2] out tri-state utopia rx data e15 rxdata[3] out tri-state utopia rx data e16 rxdata[4] out tri-state utopia rx data f14 rxdata[5] out tri-state utopia rx data f15 rxdata[6] out tri-state utopia rx data f16 rxdata[7] out tri-state utopia rx data k14 rxenb in utopia rx enable k13 rxclav out tri-state utopia rx cell available j16 rxsoc out tri-state utopia rx start of cell j15 rxclk in schmit utopia rx clock a13 c_a[0] in (inout) ctrl-e address bus b14 c_a[1] in (inout) ctrl-e address bus a14 c_a[2] in (inout) ctrl-e address bus b15 c_a[3] in (inout) ctrl-e address bus a15 c_a[4] in (inout) ctrl-e address bus c14 c_a[5] in (inout) ctrl-e address bus b16 c_a[6] in (inout) ctrl-e address bus e13 c_a[7] in (inout) ctrl-e address bus d15 c_a[8] in (inout) ctrl-e address bus b10 c_d[0] inout ctrl-e data bus a10 c_d[1] inout ctrl-e data bus b11 c_d[2] inout ctrl-e data bus a11 c_d[3] inout ctrl-e data bus b12 c_d[4] inout ctrl-e data bus a12 c_d[5] inout ctrl-e data bus c12 c_d[6] inout ctrl-e data bus b13 c_d[7] inout ctrl-e data bus c10 c_notcs in (inout) ctrl-e chip select a9 c_notwr in (inout) ctrl-e write indication a8 c_notrd in (inout) ctrl-e read indication b7 c_notrdy out tri-state ctrl-e ready indication a6 c_notint out tri-state ctrl-e interface interrupt c5 c_mode in ctrl-e mode select table 20. pin description (continued)
ST20196 26/31 ball signal name pad type description a4 u1_rxd in pull-up processor platform uart rxd b4 u1_txd out tri-state processor platform uart txd c7 u1_rts out tri-state processor platform uart rts a7 u1_cts in pull-up processor platform uart cts h16 u2_rxd in pull-up adsl tc uart rxd for fw development. ty p i c a l l y unconnected. h15 u2_txd out tri-state adsl tc uart txd h14 u2_cts in pull-up adsl tc uart cts g16 u2_rts out tri-state adsl tc uart rts c6 scan_enable in test scan enable. for test purpose. to be strapped to gnd. g15 jmode[0] in pull-up jtag ports configuration. for fw development. ty p i c a l l y unconnected. g14 jmode[1] in pull-up jtag ports configuration. a5 mode[0] in mode of operation. for test purpose. to be strapped to gnd. b6 mode[1] in a3 mode[2] in c4 ntrst in pull-down jtag port 1, reset typically connected to bscan logic. b3 tck in pull-up jtag port 1, clock b2 tms in pull-up jtag port 1, mode select a1 tdi in pull-up jtag port 1, data in d4 tdo out tri-state jtag port 1, data out j1 j2_ntrst in pull-down jtag port 2, reset for fw development. ty p i c a l l y unconnected. j2 j2_tck in pull-up jtag port 2, clock k1 j2_tms in pull-up jtag port 2, mode select k2 j2_tdi in pull-up jtag port 2, data in c1 j2_tdo out tri-state jtag port 2, data out j4 n9 h13 d8 vdd core power internally connected together h4 n8 j13 d9 vdd io power internally connected together table 20. pin description (continued)
27/31 ST20196 notes: 1. a few signals are bonded to 2 balls. keep unconnected the balls specified between parentheses. example: "h1 (h2)" ' keep un-c onnect ball h2. it will be then in line with the bsdl file that can be delivered on request. 2. some ctrl-e input pins are based on bidirectional io's for te st purpose. example: signal c_a[0] ' pad type "in (inout)". 3. decoupling strategy recommended: - vdd-io plane bulk decoupling: 10 uf - vdd-core plane bulk decoupling: 10 uf - vdd-io high frequency decoupling: 10 nf as close as possible of each respective balls - vdd-core high frequency decoupling: 10 nf as close as possible of each respective balls - vdd-pll-a: separate track with 10 uf and 10 nf decoupling - vdd-pll-d: can be connected to the same plane as vdd-core, with also the 10nf decoupling - vss-io, vss-core, vss-pll-a, vss-pll-d can be connected to a common ground plane. 4. it's recommended to foresee access to the processor platform uart (balls u1_xxx) even if not use by the application in order to allow "dsp-info" tool for prototyping debugging. ball signal name pad type description h8 j8 j9 h9 g7 h7 j7 k7 k8 k9 k10 j10 h10 g10 g9 g8 vss io/core ground internally connected together b8 vdd pll a power analog supply for pll, 3.3v b9 vdd pll d power digital supply for pll, 1.2v c9 vss pll a ground analog ground for pll, 3.3v c8 vss pll d ground digital ground for pll, 1.2v a2 d5 d6 d7 d10 c11 d11 d12 c13 d13 d14 c15 a16 unused to be kept unconnected table 20. pin description (continued)
ST20196 28/31 10 package information figure 25. lbga208 mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.210 1.700 0.048 0.067 a1 0.270 0.011 a2 1.120 0.044 b 0.450 0.500 0.550 0.018 0.020 0.022 d 16.80 17.00 17.20 0.661 0.669 0.677 d1 15.00 0.590 e 16.80 17.00 17.20 0.661 0.669 0.677 e1 15.00 0.590 e 0.90 1.00 1.10 0.035 0.039 0.043 f 0.75 1.00 1.250 0.029 0.039 0.049 ddd 0.200 0.008 lbga208 (17x17x1.70) low profile ball grid array 1 a b c d e f g h j k l m n p r t 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 bottom view a1 corner index area (see note 1) seating plane e ee1 d d1 f a a2 a1 ?b (208 balls) ddd c c lbga208m note 1 - the terminal a1 corner must be identified onthe top surface by using a corner chamfer, ink or metallized markings, or other f eature of package body or integral heatslug. - a distinguishing feature is allowable on the bottom surface of the package to identify the terminal a1 corner. - exact shape of each corner is optional. 7184626b
29/31 ST20196 11 revision history table 21. revision history date revision description of changes february 2005 1 first issue
ST20196 30/31 table of contents 1 overview ...................................................................................................................... ..................1 2 features ...................................................................................................................... ..................1 3 applications .................................................................................................................. ...............1 4 general description........................................................................................................... ......2 5 processor platform............................................................................................................ ....2 5.1 micro-controller ...........................................................................................................2 5.2 rom and boot procedure .............................................................................................3 5.3 memory interface............................................................................................................ 3 5.3.1 sdram..................................................................................................................... ........3 5.3.2 flash ..................................................................................................................... .........5 5.4 ctrl-e ...................................................................................................................... ..............6 5.4.1 ctrl-e mail box........................................................................................................... 7 5.4.2 ctrl-e semaphore.....................................................................................................8 5.4.3 ctrl-e physical interface ....................................................................................8 5.4.4 ctrl-e write access ..............................................................................................10 5.4.5 ctrl-e read access................................................................................................11 5.5 peripherals ................................................................................................................. .....12 5.5.1 watchdog .................................................................................................................. 12 5.5.2 real time counters ...............................................................................................12 5.5.3 interrupt controllers .......................................................................................12 5.5.4 uart...................................................................................................................... ........12 5.5.5 gpio controller .....................................................................................................12 6 clocking scheme ............................................................................................................... .......12 7 dmt platform .................................................................................................................. ...........12 7.1 dmt-afe (st20184) ........................................................................................................... ..12 7.1.1 dmt-afe interface signals..................................................................................13 7.1.2 dmt-afe interface timing.....................................................................................13 7.2 6.2 dmt-pmd ................................................................................................................. .......15 7.2.1 time domain processing (tdp) ............................................................................15 7.2.2 frequency domain processing (fdp) ..............................................................15 7.2.3 constellation domain processing (cdp): (de)mapper, monitor, trellis (de)coding .....15 7.2.4 fir coefficients training and tracking ........................................................16 7.2.5 clock recovery ......................................................................................................16 7.2.6 dmt symbol timing unit (dstu)............................................................................16 7.3 dmt-tc ...................................................................................................................... ...........16 7.3.1 interleaver, reed-solomon, scrambler, adsl framer ...........................17 7.3.2 atm framer................................................................................................................ 17 7.3.3 micro controller mini-platform and event counter ............................17 7.3.4 ntr ....................................................................................................................... .........17 7.4 dmt-utopia.................................................................................................................. .......17 7.4.1 utopia interface timing .......................................................................................19 8 electrical data - general specifications .....................................................................20 8.1 absolute maximum ratings.........................................................................................20 8.2 operating conditions ..................................................................................................20 8.3 power dissipation..........................................................................................................2 0 8.4 thermal characteristics, as per jedec jsd51 ...................................................20 8.5 io characteristics ........................................................................................................20 8.6 power-up sequence ......................................................................................................21 8.6.1 core-off mode .........................................................................................................21 8.6.2 io-off mode............................................................................................................... .21 9 pin description............................................................................................................... ...........23 10 package information.......................................................................................................... ....28 11 revision history ............................................................................................................. ..........29
information furnished is believed to be accurate and reliable. however, stmicroelectronics assu mes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com 31/31 ST20196

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